This invention relates to the field of integrated circuits. More particularly this invention relates to protecting integrated circuits that have more than one voltage supply.
Traditionally, all of the various components of an integrated circuit were powered from a single power source. Because all of the components were powered from the common power source, very little thought needed to be given to the effects that one component may have on another component if one of the components was powered off and the other components were powered on. This was because all of the components tended to either be powered on together or powered off together.
However, in more recent technologies, different components of an integrated circuit, such as a complimentary metal oxide semiconductor integrated circuit, are powered separately from different voltage sources. These different voltage sources have the capacity to operate independently from each other. For example, a voltage source that powers one set of components on the integrated circuit may be powered off, while a different voltage source that powers another set of components on the integrated circuit may be powered on. Thus, with different and independent voltage sources powering different portions of the integrated circuit, it becomes desirable to understand and provide for the interactions that may occur between different sets of components that are powered by the different voltage sources.
For example, in some new technologies the core of an integrated circuit, such as the memory or logic components, is powered off one voltage source, and the input output components of the integrated circuit are powered off of a different voltage source. Typically, a multi-supply integrated circuit, or in other words an integrated circuit that is powered by more than one voltage source, uses a level translator to step signals up from the core voltage levels to the input output voltage levels. Typically, the core voltage level is nominally 1.5 volts and the input output voltage level is nominally 3.3 volts.
The level translators, also called voltage level shifters, tend to have certain properties in common. One commonly shared property is that they tend to output an indeterminate state when the voltage source to the core is powered off. In other words, the shifters may provide on their outputs a logical low voltage, a logical high voltage, or a voltage that is somewhere in between when the core is powered off. Further, the shifters tend to not all have the same state on their output, but rather the many different shifters used in an integrated circuit tend to exhibit many different states, seemingly without any predictable pattern for the states that they exhibit.
Because the output of the shifters is unpredictable in this situation, the input output buffers, which are set according to the level of the output from the shifters, are also in an unpredictable state. In other words, depending upon the level of output from the shifters, the input output buffers may be driving high, driving low, or tristated. When in a tristate mode, the input output buffers are effectually electrically disconnected from other input output lines to which they are logically connected. Thus, in these multi powered integrated circuit designs, when the core power is gone, the input output buffers are left in an unknown state.
Having the input output buffers in an unknown state is generally an undesirable condition. For example, if the input output buffers are driving a state that is in conflict with another integrated circuit in the system, it could draw the short circuit current of the driver for a long period of time. This situation poses a reliability risk, not only for the integrated circuit for which the input output buffers are in an unknown state, but also for any other integrated circuit on the same system buss.
Further, when the input output buffers are in indeterminate states, such as when the core is powered down as described above, there tends to be additional reliability issues in regard to electrostatic discharge. Using the example of a conventional CMOS output buffer, a high going pin to VSS pulse typically powers up VDDIO through the p+ to n well diode. Thus, VDDIO is powered and VDDCORE is absent. At this point the level shifters have indeterminate outputs, as described above. Depending upon the predriver logic, the driver device may turn on and be damaged by the electrostatic discharge pulse:
Thus, for the various reasons as given above, it is desirable that the input output buffers not be left in an indeterminate state when the core voltage is powered off. Some integrated circuit manufacturers provide for this situation by specifying constraints on the system in terms of how power supplies must be sequenced on and off. Unfortunately, system designers tend to use integrated circuits from many different integrated circuit manufacturers, which integrated circuits further tend to have conflicting requirements for their power sequencing protocols. In some cases it may be impossible for the system designer to guarantee that different power supplies come up in a sequence specified by the integrated circuit manufacturer.
What is needed, therefore, is a system whereby the output of the voltage shifters is left in a known state when the core voltage source is powered off, so that the input output buffers can likewise be left in a known state when power to the core is lost.
The above and other needs are met by an integrated circuit having input output buffers, where the integrated circuit is powered by at least a core power supply and an input output power supply. A level shifter receives an active low signal that indicates that the core power supply has powered down. The level shifter then outputs a known state upon receipt of the active low signal. A control circuit receives the known state form the level shifter, and then tristates the input output buffers upon receipt of the known state.
In this manner, the input output buffers are tristated upon powering down of the core power supply, rather than being left in an indeterminate state as a result of the indeterminate output of the prior art level shifters. In various preferred embodiments, the active low signal is an IDDT test mode signal, the known state is a low state, and the control circuit is at least one nand gate. Preferably, the level shifter draws no direct current other than leakage current upon receipt of the active low signal. Most preferably, the control circuit is operable to tristate all of the input output buffers on the integrated circuit, while in other embodiments each of the input output buffers on the integrated circuit is tristated by a dedicated control circuit and level shifter pair.
In another aspect of the invention there is provided a method of tristating input output buffers of an integrated circuit, where the integrated circuit is powered by at least a core power supply and input output power supply. An active low signal is generated, which active low signal indicates that the core power supply has powered down. The active low signal is received with a level shifter, which outputs a known state upon receipt of the active low signal. The known state is received with a control circuit, which tristates the input output buffers upon receipt of the known state.